1. Field
The present disclosure herein relates to a computing system, and more particularly, to an apparatus and a method of managing cache coherence for a multi-processor including a plurality of cores.
2. Background
A multi-processor is one of systems often used in processing parallel programs. A cache memory to reduce a difference of a processing speed between a processor having a high speed and a main memory having a low speed is used in each of a plurality of processors included in a multi-processor.
When each processor has its own local cache and shares a memory with other processors, a data inconsistency problem may occur due to cache renewal. For example, assume that two clients have share variable X relative to a variable X and a value of the variable X is 0. At this time, if a first processor substitutes the variable X for 1 and a second processor reads the variable X, the second processor does not read the variable X having the value 1 modified by the first processor but reads the variable X having the value 0 which is now present at its local cache. Therefore, since a first cache included in the first processor and a second cache included in the second processor have different values from each other relative to the same variable X, a data inconsistency problem occurs between the first and second processors. A data coherence protocol may be applied to solve the data inconsistency problem.
In particular, in a multi-processor system using a shared memory, data coherence has to be essentially maintained. To improve an operation performance of each processor included in a multi-processor system, a method of effectively maintaining data consistency between cache memories while reducing an unnecessary waiting time of a processor and bus traffic is required.